The manufacture of thin film electronic devices (TFED) often requires that different metal systems be located in varying areas of the same substrate. While there have been a number of approaches to this problem, they all required numerous steps and precise control of the photolithography process that is often beyond the skill of the ordinary artisan. For example, some passive TFED, such as Surface Acoustic Wave (SAW) devices use metal systems that have multiple thicknesses on the same substrate to enhance performance. Precise control of the dimensions and location of the SAW metallization pattern is critical to insure optimum performance of the SAW. In other devices, such as a liquid crystal display (LCD) module, it is often desirable to mount the LCD integrated circuit (IC) driver directly to one of the glass substrates of the LCD. Wire bond or flip chip methods may be used to attach the IC die on to the glass substrate, with the flip chip technique being typically preferred because it requires less space. When wire bonds are used, additional area and volume is needed for both the wire bonds and either the lid enclosure or the polymeric glob top encapsulant material. Flip chip attachment requires that a suitable bond be formed between the integrated circuit (IC) pad metallization and the substrate metallization. For flip chip applications, the IC bond pads are either gold plated or tin-lead bumped using a well known controlled collapse chip connection (C4) process. Examples of direct chip bonding to the glass substrate is demonstrated in U.S. Pat. Nos. 4,643,526 and 4,917,466, incorporated herein by reference.
However, present IC bonding techniques such as thermocompression do not provide sufficient adhesion for providing reliable joints. It is usually necessary to selectively add subsequent metal layers such as nickel and/or gold over the indium-tin oxide (ITO) through additive vacuum deposition and following this by plating steps to achieve a bondable surface. This requires time consuming and repetitive photolithography operations to metallize the desired areas, at a significant additional expense. Alternatively, significant effort has been spent trying to attach IC's directly to the ITO metallization pattern using conductive epoxies and anisotropic conductive films. While these methods have merit, they do have limitations, especially as package densities increase and conductor lines are routed between bond pads, leaving geometries on the order of 0.0254 millimeter (0.001 inch) or less. A need thus exists in the art for a method for forming metallic areas on a substrate during fabrication which, if desired, may be overplated to provide high resolution bond sites for "chip on glass" applications. It would be advantageous if one could devise a method to achieve a highly controlled metal pattern on a substrate, while at the same time allowing one to have multiple metal thicknesses and compositions on various parts of the substrate, without the need for multiple photolithographic alignment steps. This would produce improved SAW devices, and the LCD driver IC could be directly bonded to the display .